I. Field of the Disclosure
The technology of the disclosure relates generally to static random access memory (SRAM) arrays, and particularly to designing lower power, higher performance SRAM arrays.
II. Background
Mobile communications devices have become common in contemporary society. The prevalence of these mobile devices is driven in part by the wide range of functionality provided by such devices. To achieve this wide range of functionality, mobile devices are designed to achieve lower power operation for extended battery life, while also supporting higher performance, higher power operation. The memory employed within such devices plays an important role in determining the success of achieving both lower power and higher performance operation.
In this regard, different types of memory exist, each possessing certain unique features. For example, static random access memory (SRAM) is a type of memory that can be employed in mobile communications devices. SRAM can store data without the need to periodically refresh the memory, unlike dynamic read access memory (DRAM), for example. An SRAM array contains a plurality of SRAM bit cells (also referred to as “bit cells”) organized in rows and columns. For any given row in an SRAM array, each column of the SRAM array includes an SRAM bit cell in which a single data value is stored. Access to read or write a desired SRAM bit cell row is controlled by wordlines, while data values are read from or written to particular SRAM bit cells using corresponding bitlines. An SRAM array can be designed to operate with lower power consumption, wherein such designs also operate with lower performance. Alternatively, an SRAM array can be designed to achieve higher performance operation, thus requiring higher power consumption.
An SRAM array designed to a particular performance metric employs SRAM bit cells of a corresponding design. For example, higher performance SRAM arrays employ SRAM bit cells specifically designed to operate at a higher performance level. Further, lower power SRAM arrays employ SRAM bit cells specifically designed to operate at a lower power level. To achieve varying power and performance levels in SRAM bit cells, SRAM bit cells included in an SRAM array can be designed to operate under specific parameters, such as a particular threshold voltage, number of pins, placement of pins, and metal area. In this manner, SRAM bit cells employed in lower power SRAM arrays operate according to particular design parameters that are different from parameters associated with SRAM bit cells employed in higher performance SRAM arrays. However, requiring a different SRAM bit cell design for each type of SRAM array may result in higher costs associated with design and manufacturing. Therefore, it would be advantageous to provide SRAM arrays that achieve a wide range of functionality at reduced costs.